Large scale monolithic integration of high performance electronic and photonic circuits on a single silicon chip is beginning to emerge. As reported by Graham R. Reed, “The Optical Age of Si”, Nature, Vol 247, 12 Feb. 2004, p. 595, recent advances in Si as an optical material for light emitting devices, modulators and photo-detectors, shows the possibility of silicon based electronic and photonic integrated circuits. Optical waveguides are needed to interconnect between active photonic devices.
As electronic devices and circuits are scaled down, optical waveguides and passives which interconnect among the active photonic devices, and between electronic and photonic devices, also need to be scaled down. Large index contrast waveguides with small bending radius, i.e. r<30 μm, are absolutely necessary. However, how to couple light from fiber to these miniaturized high index waveguides has been elusive. Typically, a high index difference waveguide has a substantially small mode field and very small cross section, i.e. less than 1 μm×1 μm, whereas external fibers, having a low index difference between the core and the surrounding cladding layers, have a waveguide core of approximately 8–10 micron in diameter and large mode field sizes. This mismatch in mode size between an external fiber and an on-chip high index waveguide creates a connection loss, up to 20 dB, between the planar light wave chip and the external fiber when the two are directly butt connected. An abrupt change in the refractive index at the interface between an external fiber (a low index waveguide) and an on-chip high index waveguide, also causes transmitted power loss due to the reflection of the light wave signal.
U.S. Patent Publication 2004/0037497 to Lee describes a method to resolve the coupling loss between external fibers and the miniaturized on-chip high index waveguide. He uses a double waveguide core, where the low index core is mode matched to the fiber at one end and mode matched with the embedded high index core at the other end through a mode converter. The high index core provides all the interconnecting and passive functions and then optionally couples back to the low index core and thence to an output fiber.
The mode converter is where the high index waveguide is laterally tapered, [1–2], vertically tapered, [3–4], or vertically and laterally tapered [5], depending on the mode to be matched, the tapering length, L, the tapering tip, w, the tapering height, and, hence, the taper angles. All, would have to be designed carefully to achieve minimum coupling loss—see FIG. 1
The higher index contrast waveguide has the smaller mode side and therefore, to couple light into it, the spot size of the tapering tip would be smaller. CMOS compatible processes are mainly planar, because conventional single photolithography is used, so lateral tapering is chosen for the case where the width of the tapering tip gets narrower as we mode match light from the low index core to the higher index contrast core. As reported in ref. [2], the optimum width is 1.2 μm for low index contrast of 1.5%; we calculate the optimum width for a high index contrast of 40% to be 80 nm.
In photolithography, there is a trade-off between the thickness of the photoresist and the critical dimension (CD) of the feature. To resolve small features, photoresist has to be thin. When the photoresist is thin, etching a thick waveguide and trying to get a vertical profile is very challenging. Also, we note there are other problems such as erosion of photoresist at the isolated fine tapering tip, i.e. less than 150 nm. In milder cases, the photoresist is thinner at the last section. In the worst case, the photoresist disappears completely. Moreover, photoresist on very narrow tapering tip often bends. All of these listed process problems result in much higher coupling losses.
In U.S. Pat. No. 6,420,097, “Hardmask Trim Process”, Pike describes a method to produce circuit structures having line widths which are smaller than what is achievable by conventional photolithographic techniques. The technique described enables the use of thin resist by trimming an underlying hard mask layer so that larger than required patterns can be first transferred using a conventional photolithographic technique with thin resist. However this technique requires special resist hardening processes just to perform the trimming of the hard mask itself. Furthermore, for thick dielectric stacks to be etched, particularly for photonic applications, thicker hard mask layers will need to be etched and trimmed first which will again be limited by the thickness of the photoresist available. In other words, a thicker hard mask requires thicker photoresist to etch, but with thicker photoresist we can not optically print small dimensions.
The final structure is then etched out under the trimmed hard mask. By using this method, the effect of hard mask erosion at the waveguide tips as described earlier will still be present. Though not as severe as in the case of using only photoresist as a masking layer, sidewall and tip roughening of the hard mask layer gets propagated to the target dielectric (waveguide core) layer to be etched and the roughening becomes progressively worse as the thickness of the dielectric material increases.
Another problem associated with high index contrast waveguides is surface roughness. The higher the index contrast, the greater the problem of scattering loss due to surface roughness becomes. Current smoothing techniques for Si waveguides involve oxidation of the waveguide core [6]. However, for other high index waveguides, such as SiN, smoothing by oxidation is not practical due to the very high temperature needed as well as the catalyst used which will likely affect the refractive index of the SiN core.
A major concern in the conventional photolithographic process is that trimming of such resist will not leave a sufficient amount of mask material to allow complete etching of the underlying film. FIGS. 2a through 2b illustrate a typical method of producing features which are smaller than the capabilities of conventional photolithographic methods. Seen there are substrate 11, high index core layer 21, and photoresist layer 22. FIG. 2b shows the stack after resist patterning with an initial line width (solid black line). The wafers are then subject to a trimming process which reduces the overall dimension of the resist pattern to the desired dimension (dotted line).
The reduced line width resist pattern is illustrated in FIG. 2c. The high index layer is then etched and the resist is stripped to form the final structure. FIG. 2d shows the final structure with dimensions that are smaller than what was achieved in the initial resist pattern. However, such a trimming method reduces the overall thickness of the resist pattern which inevitably causes erosion of the waveguide tip where the line width is smallest (<0.25 μm) as well as roughening of the waveguide side wall during the high index layer etching process. This problem becomes more prominent when a thick (>3000 Å) high index layer needs to be etched. A thicker layer of resist may be used to overcome this problem. However, the use of thicker resist films limits the photo stepper's ability to resolve smaller features. Further trimming of the resist to achieve the desired dimensions again repeats the problem of reducing the resist thickness.
FIGS. 3a to 3e illustrate an alternative method of producing features that are smaller than what is achievable with conventional photo lithographic methods. Seen there are hard mask layer 32, high index core layer 33, and low index cladding layer 34. In this method, the patterned resist 31, as illustrated in FIG. 3a, has to undergo another special resist hardening process to minimize resist loss during the subsequent hard mask anisotropic etch (FIG. 3b). This is followed by an isotropic trimming process of the hard mask layer 32 (FIG. 3c) to achieve a smaller line width feature than what was initially achieved during the resist patterning process. The resist 31 is then stripped (FIG. 3d), followed by the main etch of the high index layer 33 (FIG. 3e).
This method has several disadvantages. Trimming down the hard mask to the desired line width at such an early stage subjects the high index layer to erosion at the waveguide tip during the etching process. The hard mask may be more resistant to the etching plasma when compared to conventional photoresist but, for very small waveguide tip features, there is a tendency for the tips of the hard mask to be eroded much more quickly than the wider areas. The end result would be poorly defined waveguide tip features with very rough side walls.
This sort of problem becomes more serious when thick (>3,000 Å) high index layers have to be etched. The use of a thicker hard mask layer to overcome this sort of problem will indirectly require a thicker layer of patterned resist to ensure sufficient protection for a complete etch of the hard mask. The thicker resist layer will also further limit the smallest feature size achievable by the lithography tool.
Another disadvantage of this method is that there are no provisions for smoothing of the high index waveguide walls. The severity of the inherent side wall roughening during the etching process depends on both the quality of the patterning technique used, as well as the high index layer material used. Side wall roughening of the waveguides results in scattering losses, which leads to higher light transmission losses and therefore must be reduced by a smoothing process. Yet another disadvantage of this method is that special resist hardening processes and equipment are needed for the successful trimming of the hard mask which adds cost to the entire production cycle.